The present invention relates to semiconductor processing and integrated circuits in general, and, more particularly, to integrated circuits that are susceptible to ionizing radiation.
As is well known in the prior art, older semiconductor processing technologies produced integrated circuits that were highly susceptible to damage from ionizing radiation. Such ionizing radiation is emitted from galactic sources (e.g., the Sun, stars, pulsars, quasars, black holes, etc.) and exists above the ionosphere. Ionizing radiation is also emitted when nuclear weapons are detonated.
The mechanism by which ionizing radiation affects the electrical characteristics of CMOS and NMOS transistors and other semiconductor devices is described in detail below in conjunction with FIGS. 1A through 1C. A summary of the mechanism is as follows.
Under normal operating conditions, the threshold voltage, VT, of an n-type transistor is normally and advantageously high. When an n-type transistor is exposed to ionizing radiation, the ionizing radiation causes the threshold voltage, VT, of the transistor to fall, which can cause the transistor to operate abnormally. If an n-type transistor is exposed to a sufficiently large total dose of ionizing radiation, then the threshold voltage can fall so low that the transistor continuously conducts current between the source and drain. This causes the transistor to fail completely and typically destroys the operation of the integrated circuit of which it is a part.
A detailed understanding of the mechanism by which ionizing radiation affects CMOS and NMOS transistors requires and understanding of the physical and electrical structure of an n-type transistor.
An n-type transistor, such as that depicted in FIGS. 1A through 1C, comprises two distinct xe2x80x9ctransistorsxe2x80x9d that are electrically in parallel: (1) an xe2x80x9coperatingxe2x80x9d transistor, and (2) a xe2x80x9cparasiticxe2x80x9d transistor.
The operating transistor is the intended ideal structure for regulating the flow of current between the source and drain. The parasitic transistor is an unintended, but real transistor structure that results from artifacts in the manufacture of the operating transistor and from the fact that the materials used to build the operating transistor do not function perfectly. The operating transistor and the parasitic transistor each have their own threshold voltage, VT. Because the operating transistor and the parasitic transistor are in parallel, the one with the lower threshold voltage, VT, is the one that effectively overrules the operation of the other. For the purposes of this specification, the xe2x80x9ceffective threshold voltagexe2x80x9d of a transistor is defined as the lower of (i) its operating transistor""s threshold voltage and (ii) its parasitic transistor""s threshold voltage.
Under normal operating conditions, the threshold voltage of the parasitic transistor is higher than the threshold voltage of the operating transistor, and, therefore, the current flow between the source and the drain is regulated by the operating transistor. This is the desired condition.
In contrast, when the transistor has been exposed to a high dose of ionizing radiation, the threshold voltage of the parasitic transistor can fall below that of the operating transistor. In fact, the threshold voltage of the parasitic transistor can fall so low that it becomes a xe2x80x9cclosedxe2x80x9d circuit, which effectively shorts the source and drain regardless of the state of the operating transistor. This is the abnormal condition. As stated above, when the source and drain are effectively shorted together regardless of the state of the operating transistor, the transistor fails completely and most likely destroys the operation of the integrated circuit of which it is a part.
FIG. 1A depicts a plan view of n-type transistor 102, which comprises: n-type drain region 104, n-type source region 106, and gate electrode 108, (e.g., polysilicon, etc.). Drain region 104 and source region 106 are bounded by field oxide 112, (e.g., silicon dioxide, etc.), which help electrically isolate transistor 102 from other transistors that might be near it (and are not shown in FIG. 1A).
FIG. 1B is a cross-section of transistor 102 along line Ixe2x80x94I (as shown in FIG. 1A) as viewed in the direction indicated and depicts the germane portions of the operating transistor. The operating transistor comprises: gate electrode 108 which overlies gate dielectric 118 and channel region 110 in p-type substrate 114 between drain region 104 and source region 106.
FIG. 1C is a cross-section of transistor 102 along line IIxe2x80x94II (as shown in FIG. 1A) as viewed in the direction indicated and depicts the germane portions of the parasitic transistor. The parasitic transistor comprises: gate electrode 108 which overlies field oxide 112/p-type substrate 114 at regions 120, wherein field oxide 112 forms a shape similar to a bird""s beak. Typically, p-type regions 116 are more heavily-doped than substrate 114 to increase the threshold voltage of the parasitic transistor, which is advantageous because it helps to ensure that the threshold voltage of the operating transistor is higher than the threshold voltage of the parasitic transistor.
As stated above, the exposure of an n-type transistor to ionizing radiation can change the threshold voltage, VT, of both the operating transistor and the parasitic transistor. The threshold voltage, VT, of either is theoretically predicted by the following equation:
VT=xcfx86xe2x88x92("sgr"/xcex5)dxe2x88x92Fxe2x80x83xe2x80x83(Eq.1)
where: xcfx86 is the work function of the gate region; "sgr" is the total charge at the dielectric(insulator)-semiconductor interface; xcex5 is the dielectric constant of the insulator; d is the insulator thickness; and F is a term that can be considered a constant.
If, somehow, positive interface charge, "sgr", is added at the dielectric(insulator)-semiconductor interface, then the threshold voltage, VT, decreases. One way of adding positive interface charge, "sgr", to the device is to expose it to ionizing radiation. It can be seen from Equation 1 that with a sufficient increase in the positive interface charge, "sgr", an n-type transistor can have an effective threshold voltage, VT, of zero.
When an n-type transistor is exposed to ionizing radiation, electron-hole pairs are formed in the gate dielectric and the field oxide. Some of the holes become trapped in the gate dielectric and field oxide as various gate-induced fields sweep out the electrons as part of normal circuit operation. Because holes behave like positive charge, this phenomenon is referred to as positive-charge trapping. Although the electrons are swept out of the circuit, the trapped xe2x80x9cpositivexe2x80x9d charges migrate toward the dielectric(insulator)-semiconductor interface, which adds positive interface charge, "sgr", and decreases the effective threshold voltage, VT, of the transistor.
Because the field oxide traps more positive charge than the gate dielectric, and because the threshold voltage decreases as the positive interface charge increases, the threshold voltage of the parasitic transistor at regions 120 will therefore shift downwardly more than will the threshold voltage of the operating transistor (i.e., the transistor having gate dielectric 118) when exposed to the same amount of ionizing radiation. If the dose of radiation is sufficiently great, the parasitic transistor will conduct at regions 120 (i.e., under the edge of field oxide 112) when the operating transistor normally conducts. Therefore, the parasitic transistor is more susceptible to ionizing radiation than is the operating transistor.
The important consequence of the susceptibility of integrated circuits to ionizing radiation is that they are not well suited for use in satellites or in military applications, and, therefore, they can be freely sold and exported without creating the fear that they can be used militarily against the United States or its allies.
In contrast, some state-of-the-art semiconductor processing technologies produce integrated circuits whose operating transistors and parasitic transistors are inherently highly tolerant to damage from ionizing radiation. The reason is because the smaller feature sizes of contemporary semiconductor processing technologies trap fewer positive charges than the larger feature sizes of older processing technologies.
Although the relatively high radiation tolerance of state-of-the-art integrated circuits is of no benefit to most users and for most applications, it makes the circuits suitable for use in aerospace and military applications. This, of course, justifies the fear that they could be used militarily against the United States or its allies, and so the Department of Defense export restrictions (ITAR) might prevent those chips from being freely sold or exported. To the extent that a commercial CMOS or NMOS fabricator is restricted by ITAR from freely selling or exporting chips that have a legitimate non-military use, it suffers financially.
Therefore, the need exists for a technique that increases the susceptibility of integrated circuits to ionizing radiation, but that retains the other advantages that accrue from contemporary processing methods.
Some embodiments of the present invention provide integrated circuits that have increased susceptibility to ionizing radiation without the costs and disadvantages of techniques in the prior art. In particular, the illustrative embodiment of the present invention is an integrated circuit that possesses the benefits of contemporary processing technologies (e.g., small feature size, etc.) yet is advantageously irreparably damaged by ionizing radiation. Thus, some integrated circuits made in accordance with the present teachings can be freely sold and exported without creating the justifiable fear that they can be used militarily against the United States or its allies.
In accordance with the illustrative embodiment of the present invention, an integrated circuit is designed and fabricated with contemporary processing technologies in well-known fashion, except that certain devices, called xe2x80x9csafeguardxe2x80x9d devices, are added to the integrated circuit. The safeguard devices are fabricated so that they, and not the other devices on the integrated circuit, are susceptible to ionizing radiation. Furthermore, the safeguard devices are coupled into the logic of the integrated circuit in such a manner than when the integrated circuit is bombarded with ionizing radiation the safeguard devices irreparably destroy the functionality of the integrated circuit.
In general, the safeguard devices can destroy the functionality of the integrated circuits in two ways. First, one or more safeguard devices can interfere with the logical operation of an integrated circuit by, for example, shorting a signal lead to ground. This, of course, interferes with the logical operation of the integrated circuit.
Second, one or more safeguard devices can interfere with the electrical operation of an integrated circuit by, for example, shorting VDD to ground. This technique works, of course, by depriving the utile devices on the integrated circuit of electrical power.
The first illustrative embodiment of the present invention is an integrated circuit comprising: a first device comprising a first lead, a second lead, and a third lead, wherein the third lead of the first device is electrically connected to ground; and a second device comprising a first lead, a second lead, and a third lead, wherein the third lead of the second device is electrically connected to ground; wherein the effective threshold voltage of the first device is more susceptible to be lowered by ionizing radiation than is the effective threshold voltage of the second device.
In a first variation of the first illustrative embodiment, the integrated circuit wherein the first device comprises an n-type metal-oxide semiconductor field-effect transistor.
In a second variation of the first illustrative embodiment, the first device comprises a field oxide that has been implanted with a material that traps positive charge when the first device is exposed to ionizing radiation and the second device has not been implanted with the material.
In a third variation of the first illustrative embodiment, the integrated circuit comprises a microprocessor that comprises a control sequencer and arithmetic logic unit.
In a fourth variation of the first illustrative embodiment, the integrated circuit comprises a plurality of memory cells.
In a fifth variation of the first illustrative embodiment, the second lead of the first device is connected to ground, the third lead of the first device is connected to power, and the third lead of the second device is connected to power.
In a sixth variation of the first illustrative embodiment, the first device shorts power to ground when the device has been exposed to ionizing radiation.
The second illustrative embodiment of the present invention is an integrated circuit comprising: a first device comprising a first lead, a second lead, and a third lead, wherein the third lead of the first device is electrically connected to ground; and a second device comprising a first lead, a second lead, and a third lead, wherein the third lead of the second device is electrically connected to ground; wherein at least a portion of the first device comprises a higher concentration of positive charge trapping centers than the second device.
In a first variation of the second illustrative embodiment, the first device comprises an n-type metal-oxide semiconductor field-effect transistor.
In a second variation of the second illustrative embodiment, the integrated circuit comprises a microprocessor that comprises a control sequencer and arithmetic logic unit.
The third illustrative embodiment of the present invention is a method comprising: fabricating a base layer comprising a first device having a first lead and a second lead, and a second device having a first lead that is electrically connected to the first lead of the first device; implanting at least a portion of the first device with a material that traps positive charge when the first device is exposed to ionizing radiation; and preventing the second device from being implanted with the material.
In a first variation of the third illustrative embodiment, the first device comprises an n-type metal-oxide semiconductor field-effect transistor.
In a second variation of the third illustrative embodiment, there is a field oxide in an isolation region associated with the first device is implanted with the material.
The third variation of the third illustrative embodiment further comprises masking the base layer with a resist to protect the second device from being implanted with the material and to expose the first device to being implanted with the material.
The fourth illustrative embodiment of the present invention is a method comprising: fabricating a base layer comprising a first device having a first lead and a second lead, and a second device having a first lead that is electrically connected to the first lead of the first device; masking the base layer with a resist to protect the second device from an implantation that traps positive charge when the second device is exposed to ionizing radiation, and to expose the first device to the implantation; and implanting at least a portion of the first device with the implantation.
In a first variation of the fourth illustrative embodiment, the first device comprises an n-type metal-oxide semiconductor field-effect transistor.
In a second variation of the fourth illustrative embodiment, there is a field oxide in an isolation region associated with the first device is implanted with the material.
The fifth illustrative embodiment of the present invention is a method of operating an integrated circuit, the method comprising: processing signals with a first device; and interfering with the operation of the first device with a second device when and only when the integrated circuit is exposed to ionizing radiation.
In a first variation of the fifth illustrative embodiment, the exposure of the integrated circuit to ionizing radiation shorts an output of the first device to ground through the second device.
In a second variation of the fifth illustrative embodiment, at least a portion of the second device comprises an implant that facilitates the trapping of positive charge when exposed to ionizing radiation that the first device does not comprise.
In a third variation of the fifth illustrative embodiment, the exposure of the integrated circuit to ionizing radiation disables the operation of the integrated circuit.